Power amplifying apparatus, power combining system and delay measuring method for power combining system

ABSTRACT

A power amplifying apparatus includes a distributing unit that divides an input digital signal to a plurality of the input digital signals so as to distribute the input digital signals to a plurality of devices respectively, and a synthesizing unit that synthesizing output signals from the devices to output the synthesized output signal. Each of the devices includes a delay regulating unit that regulates a delay amount of the input digital signal, a digital/analog converting unit that converts the digital signal regulated by the delay regulating unit to an analog signal, and an amplifying unit that amplifies the analog signal to output the amplified analog signal to the synthesizing unit.

TECHNICAL FIELD

The present invention relates to a power amplifying apparatus, a powercombining system and a delay regulating system for the power combiningsystem.

BACKGROUND ART

A very high output is required for a power amplifying apparatus to beused in a mobile base station or a transmitter for broadcasting. Forexample, one output reaches 40 to 80W in a base station for WCDMA andreaches several kW in equipment for digital broadcasting. In such atransmitter, one power amplifier device cannot cover a single amplifierunit. For this reason, it is necessary to connect several devices oramplifier units in parallel.

FIG. 5 is a diagram showing the schematic structure of a poweramplifying apparatus using a power combining system. As shown in FIG. 5,an input signal is distributed to a plurality of systems (paralleldevices) by a distributor 101, and the signals thus distributed areamplified by power amplifiers 102 a to 102 c in the parallel units(devices) respectively and a signal synthesized by a synthesizer 103 isoutput. In such a conventional power combining system, it is necessaryto accurately control the group delay of each parallel unit or device.For the most basic method for carrying out the group delay, a delay lineis used in each parallel unit.

However, it is very hard to manufacture and regulate a parallel powercombining system using the delay line in order to match the delays ofthe parallel units. In the case in which the regulation is notsufficient, a synthetic output power is attenuated or a frequencycharacteristic is generated on an output.

If an analog signal is input, moreover, it is possible to carry out agroup delay measurement for a delay between an input and an output byusing a network analyzer and to theoretically obtain the length of thedelay line from a measured value (delay amount).

In an amplifier using such a parallel power combining system, however,an input is digital in a system using a digital predistortion (forexample, JP-A-2003-332853), an EER (Envelope Elimination andRestoration) and an LINC (Linear amplification with Non-linearComponents). Therefore, it is also impossible to carry out a group delaymeasurement using such as the network analyzer.

DISCLOSURE OF THE INVENTION

In consideration of the conventional circumstances, it is an object ofthe invention to provide a power amplifying apparatus and a powercombining system capable of easily regulating a delay and a delaymeasuring method for the power combining system.

In order to achieve the above object, according to the presentinvention, there is provided a power amplifying apparatus, comprising:

a distributing unit that divides an input digital signal to a pluralityof the input digital signals so as to distribute the input digitalsignals to a plurality of devices respectively; and

a synthesizing unit that synthesizing output signals from the devices tooutput the synthesized output signal, wherein each of the devicesincludes:

-   -   a delay regulating unit that regulates a delay amount of the        input digital signal;    -   a digital/analog converting unit that converts the digital        signal regulated by the delay regulating unit to an analog        signal; and    -   an amplifying unit that amplifies the analog signal to output        the amplified analog signal to the synthesizing unit.

By this structure, it is possible to easily regulate a delay in thepower amplifying apparatus requiring the high outputs of a digital inputand an analog output.

Preferably, the delay regulating unit includes a shift register in whichthe number of stages is variable. The delay regulating unit adjusts thenumber of stages of the shift register to regulate the delay amount ofthe input digital signal.

Consequently, it is possible to easily regulate a delay with a simplestructure.

Preferably, the power amplifying apparatus further includes an inputclock control unit that controls a phase of an input clock signal of thedigital/analog converting unit of each of the devices.

By this structure, it is possible to control a delay with a highresolution by controlling the phase of an input clock signal when thesampling frequency of the input clock of the digital/analog convertingunit is low.

Preferably, the delay regulating unit includes a digital filter. Thedelay regulating unit adjusts a filter coefficient of the digital filterto regulate the delay amount of the input digital signal.

Consequently, it is possible to easily regulate a delay with a simplestructure when the sampling rate of the digital/analog converting unitis low.

According to the present invention, there is also provided a powercombining system, comprising:

a distributing unit that divides an input digital signal to a pluralityof the input digital signals so as to distribute the input digitalsignals to a plurality of devices respectively; and

a synthesizing unit that synthesizing output signals from the devices tooutput the synthesized output signal;

wherein each of the devices includes:

-   -   a delay regulating unit that regulates a delay amount of the        input digital signal;    -   a digital/analog converting unit that converts the digital        signal regulated by the delay regulating unit to an analog        signal; and    -   an amplifying unit that amplifies the analog signal to output        the amplified analog signal to the synthesizing unit,

the power combining system, further comprising:

a measuring unit that acquires at least one of an output power and afrequency characteristic of the synthesized output signal to measure adelay between the devices; and

a control unit that controls the delay regulating unit so as to regulatethe delay amount of the input digital signal based on the measured delaybetween the devices.

According to the present invention, there is also provided a delaymeasuring method for a power combining system including a plurality ofdevices, digital input signals being distributed to the devices, andanalog output signals from the devices being synthesized to asynthesized output signal, the delay measuring method comprising:

acquiring at least one of an output power and a frequency characteristicof the synthesized output signal; and

measuring a delay between the devices based on the at least one of theoutput power and the frequency characteristic of the synthesized outputsignal.

By this method, it is possible to measure a delay amount in the powercombining system for the digital input and the analog output.

According to the invention, it is possible to provide a power amplifyingapparatus and a power combining system capable of easily regulating adelay and a delay measuring method for a power combining system.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore apparent by describing in detail preferred exemplary embodimentsthereof with reference to the accompanying drawings, wherein:

FIG. 1 is a diagram showing the schematic structure of a digitaldistortion compensation amplifying apparatus according to a firstembodiment of the invention;

FIG. 2 is a diagram showing the schematic structure of a digitaldistortion compensation amplifying apparatus according to a secondembodiment of the invention;

FIG. 3 is a diagram showing the schematic structure of a digitaldistortion compensation amplifying apparatus according to a thirdembodiment of the invention;

FIG. 4 is a diagram showing the schematic structure of a delay measuringsystem according to a fourth embodiment of the invention; and

FIG. 5 is a diagram showing the schematic structure of a poweramplifying apparatus using a power combining system.

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment

FIG. 1 is a diagram showing the schematic structure of a digitaldistortion compensation amplifying apparatus according to a firstembodiment of the invention. As shown in FIG. 1, the digital distortioncompensation amplifying apparatus according to the first embodimentcomprises a distributor 10, digital predistortion portions (hereinafterreferred to as DPDs) 20 a, 20 b and 20 c, variable shift registers(hereinafter referred to as VSRs) 31 a, 31 b and 31 c, digital/analogconverters (hereinafter referred to as DACs) 40 a, 40 b and 40 c, upconverters (hereinafter referred to as UPCS) 50 a, 50 b and 50 c, poweramplifiers 60 a, 60 b and 60 c, and a synthesizer 70.

Next, description will be given to the operation of the digitaldistortion compensation amplifying apparatus according to the firstembodiment. The distributor 10 is an example of a distributing unit andserves to distribute a digital signal input to the digital distortioncompensation amplifying apparatus to a plurality of systems (devices).In the embodiment according to the invention, description will be givenby taking, as an example, the case in which an input signal isdistributed to three systems in total, that is, a system A, a system Band a system C so as to be amplified.

The DPDs 20 a, 20 b and 20 c provided in the systems (the systems A, Band C) respectively carry out a predistortion processing of adding thereverse characteristics of the distortions of the distortioncompensation power amplifiers 60 a, 60 b and 60 c to baseband digitalsignals distributed by the distributor 10, for example. Thepredistortion processing is carried out by giving a clock signal (CLK)having a predetermined sampling frequency.

The VSRs 31 a, 31 b and 31 c are an example of a delay regulating unitand serve to give predetermined delay amounts to the signals subjectedto the predistortion processing by the DPDs 20 a, 20 b and 20 c and tooutput the same signals, respectively.

The DACs 40 a, 40 b and 40 c are an example of a digital/analogconverting unit and serve to convert the signals output from the VSRs 31a, 31 b and 31 c from digital signals to analog signals by setting apredetermined sampling frequency as an input clock, respectively. TheUPCs 50 a, 50 b and 50 c convert the analog signals output from the DACs40 a, 40 b and 40 c from a baseband to a radio frequency (RF) bandrespectively, for example.

The power amplifiers 60 a, 60 b and 60 c are an example of an amplifyingunit and serve to amplify the signals output from the UPCs 50 a, 50 band 50 c, respectively. The synthesizer 70 is an example of asynthesizing unit and serves to synthesize and output signals sent fromthe power amplifiers 60 a, 60 b and 60 c, that is, signals sent from thesystems A, B and C.

In the digital distortion power amplifying apparatus according to thefirst embodiment, the VSRs 31 a, 31 b and 31 c are inserted asvariable-length buffers before the DACs as described above. By adjustingthe number of stages of the VSRs 31 a, 31 b and 31 c, it is possible toregulate the delay amount of each of the systems.

A delay control amount C₁ (from the output end of the DPD to the inputend of the DAC) is expressed in Equation (1), wherein the samplingfrequency of the DAC is represented by f_(s) and the number of stages ofthe VSR is represented by n.C ₁=1/f _(s) ·n  (1)

In the case in which the delay regulation is carried out for a signal ina microwave band, the delay control amount is in ns (nanosecond) order.Therefore, the sampling frequencies of the DACs 40 a, 40 b and 40 crequire approximately 1 GHz.

According to the first embodiment of the invention, it is possible toeasily regulate a delay with a simple structure in the power amplifyingapparatus for the digital input/analog output of a power combiningsystem.

While the description has been given to the case in which the digitalbaseband predistortion is used in each system in the embodiment, a poweramplifying apparatus for a digital input/analog output, for example, apower amplifying apparatus using an EER and an LINC can produce anadvantage that a delay can easily be regulated.

Second Embodiment

FIG. 2 is a diagram showing the schematic structure of a digitaldistortion compensation amplifying apparatus according to a secondembodiment of the invention. In FIG. 2, overlapping portions with thosein FIG. 1 described in the first embodiment have the same referencenumerals.

As shown in FIG. 2, in the digital distortion compensation amplifyingapparatus according to the second embodiment, FIR (Finite ImpulseResponse) filters 32 a, 32 b and 32 c are provided in the former stagesof DACs 40 a, 40 band 40 c as an example of a delay regulating unit.

By providing the FIR filters 32 a, 32 b and 32 c for a delay regulation,it is possible to carry out the delay regulation also in the case inwhich the DACs 40 a, 40 b and 40 c having lower sampling frequencies areused. In this case, a coefficient control is carried out to perform anoversampling design over the FIR filters 32 a, 32 b and 32 c in order toobtain a necessary delay regulating resolution.

The FIR filters 32 a, 32 b and 32 c control the coefficients so that adelay amount can be regulated. For the FIR filters, a processing time isgenerated depending on the number of filter stages.

A control delay amount C₂ (from the output end of a DPD to the input endof the DAC) is expressed in Equation (2), wherein the number of filterstages of the FIR filter is represented by m, a delay amount based on acoefficient control is represented by D_(f), and the sampling frequencyof the DAC is represented by f_(s).C ₂=(m+D _(f))·1/f _(s)  (2)

By carrying out a design to oversample the sampling rate of the FIRfilter, accordingly, a desirable delay regulation can be implementedeven if the DAC having a low sampling rate is used.

According to the second embodiment of the invention, it is possible toeasily carry out a delay regulation with a simple structure also in thecase in which the sampling frequency of an analog conversion is low inthe power amplifying apparatus for the digital input/analog output of apower combining system.

Third Embodiment

FIG. 3 is a diagram showing the schematic structure of a digitaldistortion compensation amplifying apparatus according to a thirdembodiment of the invention. In FIG. 3, overlapping portions with thosein FIG. 1 described in the first embodiment have the same referencenumerals.

As shown in FIG. 3, the digital distortion compensation amplifyingapparatus according to the third embodiment is provided with a DDS(Direct Digital Synthesizer) 33 for controlling an input clock signalCLK of DACs 40 a, 40 b and 40 c.

The DDS 33 is an example of an input clock control unit and is a circuitcapable of converting an input frequency to an optional frequency withina range of at most ½ on the basis of a frequency which is several timesas great as the frequencies of the input clock signals (CLK) of the DACs40 a, 40 b and 40 c.

In the digital distortion compensation amplifying apparatus according tothe embodiment, the DDS 33 is used as a circuit for changing an initialphase with respect to a sampling frequency without varying the frequencyof the input clock signal (a sampling frequency). Consequently, a phasecontrol can be carried out for one wavelength in a resolution ofapproximately one-thousandth. Therefore, it is possible to control adelay in the width of the number of stages of a VSR with a resolution ofone-thousandth of a sampling rate by using VSRs 31 a, 31 b and 31 ctogether.

A delay control amount C₃ (from the output end of a DPD to the input endof an amplifier) is expressed in Equation (3), wherein the samplingfrequency of the DAC is represented by f_(s), the number of stages ofthe VSR is represented by n, and the phase control amount of the DDS isrepresented by C.C ₃=1/f _(s)·(n+C)  (3)

Accordingly, such a rough regulation as to correspond to the samplingfrequency is carried out by the control of the number of stages of theVSR, and furthermore, a fine regulation is performed by the execution ofa delay regulation through the phase control of the DDS. Also in thecase in which the DAC having a low sampling frequency is used,therefore, a sufficient delay regulation can be carried out. Moreover,the delay is not regulated by a filter. Consequently, it is possible tocontrol a delay amount without reducing the band of an input signal.

According to the third embodiment of the invention, it is possible toeasily carry out the delay regulation with a simple structure also inthe case in which the sampling frequency of an analog conversion is lowin a power amplifying apparatus for the digital input/analog output of apower combining system.

Fourth Embodiment

FIG. 4 is a diagram showing the schematic structure of a delay measuringsystem according to a fourth embodiment of the invention. In FIG. 4,overlapping portions with those in FIGS. 1 to 3 described in the firstto third embodiments have the same reference numerals.

As shown in FIG. 4, a power combining system has a distributor 10, aplurality of systems 1 a to 1 c, and a synthesizer 70. The distributor10 serves to distribute an input digital signal to a plurality ofsystems (three systems A to C in the embodiment). The systems A (1a), B(1b) and C (1c) have a digital/analog converting function and outputdigital signals, respectively. The synthesizer 70 synthesizes andoutputs the signals sent from the systems A to C (1a to 1c). Morespecifically, in the power combining system according to the embodiment,a digital signal is input and an analog signal is output.

The output signal of the power combining system is measured by a powermeter 81 and a spectrum analyzer 82, thereby measuring the matchingstates of the delays of the systems A to C (1a to 1c).

The power meter 81 measures the output power level of the synthesizer70. In the case in which the delays of the systems A to C cannot bematched well, the output power level is more lowered than that in thecase in which the delays are matched. By acquiring the same outputlevel, accordingly, it is possible to measure the matching states of thedelays between the systems.

The spectrum analyzer 82 measures the frequency characteristic of asignal output from the synthesizer 70. In the case in which the delaysof the systems A to C cannot be matched well, a flatness is varied overthe frequency characteristic of the output signal in the vicinity of acarrier frequency. By acquiring the frequency characteristic of theoutput signal, accordingly, it is possible to measure the matchingstates of the delays between the systems.

Also in the power combining system for the digital input/analog output,consequently, it is possible to properly measure a delay.

In the case in which the systems A to C have a delay regulatingfunction, there is provided a control signal generating portion 90 forgenerating a control signal for the delay regulating function based onthe results of the measurement of the power meter 81 and the spectrumanalyzer 82 as shown in FIG. 4. Consequently, it is possible to easilyregulate a delay.

The control signal generating portion 90 generates a control signal toregulate the delay amount of each system in such a manner that an outputlevel to be measured is maximized for the result of the output of thepower meter 81. Moreover, a control signal to cause a frequencycharacteristic to be measured to be flatter is generated for the resultof the output of the spectrum analyzer 82.

Examples of the regulating method include a method for fixing any of thesystems and sequentially regulating the delays of the other systems,thereby regulating the delay.

The control signal generated by the control signal generating portion 90is a coefficient control signal to be input to the VSRs 31 a to 31 c ifthe circuits of the systems A to C (1a to 1c) are the systems A to Caccording to the first embodiment, is a stage number control signal tobe input to the FIRs 32 a to 32 c if the same circuits are the systems Ato C according to the second embodiment, and is a coefficient controlsignal to be input to the VSRs 31 a to 31 c and a phase control signalto be input to the DDS 33 if the same circuits are the systems A to Caccording to the third embodiment, for example.

Referring to the results of the measurement of the power meter 81 andthe spectrum analyzer 82, a high correlation can be observed for thedelay matching states between the systems. Accordingly, it is possibleto measure the delay by only one of the power meter 81 and the spectrumanalyzer 82. By carrying out the measurement through both of them, it ispossible to measure the delay more reliably.

According to the fourth embodiment of the invention, it is possible tomeasure a delay in the power combining system, and furthermore, toeasily regulate the delay amount of each system based on the measureddelay.

Although the invention has been illustrated and described for theparticular preferred embodiments, it is apparent to a person skilled inthe art that various changes and modifications can be made on the basisof the teachings of the invention. It is apparent that such changes andmodifications are within the spirit, scope, and intention of theinvention as defined by the appended claims.

The present application is based on Japan Patent Application No.2004-239220 filed on Aug. 19, 2004, the contents of which areincorporated herein for reference.

INDUSTRIAL APPLICABILITY

The power amplifying apparatus and the delay measuring method for apower combining system according to the invention have an advantage thata delay can easily be regulated, and are useful for a mobile basestation or a transmitter for broadcasting.

1. A power amplifying apparatus, comprising: a distributing unit thatdivides an input digital signal to a plurality of the input digitalsignals so as to distribute the input digital signals to a plurality ofdevices respectively; and a synthesizing unit that synthesizing outputsignals from the devices to output the synthesized output signal,wherein each of the devices includes: a delay regulating unit thatregulates a delay amount of the input digital signal; a digital/analogconverting unit that converts the digital signal regulated by the delayregulating unit to an analog signal; and an amplifying unit thatamplifies the analog signal to output the amplified analog signal to thesynthesizing unit.
 2. The power amplifying apparatus as set forth inclaim 1, wherein the delay regulating unit includes a shift register inwhich the number of stages is variable; and wherein the delay regulatingunit adjusts the number of stages of the shift register to regulate thedelay amount of the input digital signal.
 3. The power amplifyingapparatus as set forth in claim 2, further comprising an input clockcontrol unit that controls a phase of an input clock signal of thedigital/analog converting unit of each of the devices.
 4. The poweramplifying apparatus as set forth in claim 1, wherein the delayregulating unit includes a digital filter; and wherein the delayregulating unit adjusts a filter coefficient of the digital filter toregulate the delay amount of the input digital signal.
 5. A powercombining system, comprising: a distributing unit that divides an inputdigital signal to a plurality of the input digital signals so as todistribute the input digital signals to a plurality of devicesrespectively; and a synthesizing unit that synthesizing output signalsfrom the devices to output the synthesized output signal; wherein eachof the devices includes: a delay regulating unit that regulates a delayamount of the input digital signal; a digital/analog converting unitthat converts the digital signal regulated by the delay regulating unitto an analog signal; and an amplifying unit that amplifies the analogsignal to output the amplified analog signal to the synthesizing unit,the power combining system, further comprising: a measuring unit thatacquires at least one of an output power and a frequency characteristicof the synthesized output signal to measure a delay between the devices;and a control unit that controls the delay regulating unit so as toregulate the delay amount of the input digital signal based on themeasured delay between the devices.
 6. A delay measuring method for apower combining system including a plurality of devices, digital inputsignals being distributed to the devices, and analog output signals fromthe devices being synthesized to a synthesized output signal, the delaymeasuring method comprising: acquiring at least one of an output powerand a frequency characteristic of the synthesized output signal; andmeasuring a delay between the devices based on the at least one of theoutput power and the frequency characteristic of the synthesized outputsignal.